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DEVICE SPECIFICATION
SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL OC-48 TRANSMITTER AND CLOCK GENERATOR SONET/SDH/ATM OC-12 16:1 TRANSMITTER RECEIVER GENERAL DESCRIPTION
S3083 S3083 S3083
FEATURES
* Micro-power Bipolar supply * Complies with Bellcore and ITU-T specifications * On-chip high-frequency PLL for clock generation * Supports 2.488 Gbps (OC-48) * Reference frequency of 155.52 MHz * Interface to both LVPECL and LVTTL logic * 16-bit LVPECL data path * Compact 80 PQFP/TEP package * Diagnostic loopback mode * Line loopback * Lock detect * Low jitter LVPECL interface * Internal FIFO to decouple transmit clocks * Single 3.3V supply
The S3083 SONET/SDH MUX chip is a fully integrated serialization SONET OC-48 (2.488 Gbps) interface device. The chip performs all necessary parallel-to-serial functions in conformance with SONET/SDH transmission standards. The device is suitable for SONETbased ATM applications. Figure 1 shows a typical network application. On-chip clock synthesis PLL components are contained in the S3083 MUX chip allowing the use of a slower external transmit clock reference. The chip can be used with 155.52 MHz reference clock, in support of existing system clocking schemes. The low jitter LVPECL interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3083 is packaged in a 80 PQFP/TEP, offering designers a small package outline.
APPLICATIONS
* * * * * * * * * * SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH DWDM Systems Section repeaters Add Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1. System Block Diagram
Network Interface Processor
16
S3083 Tx S3044 Rx
OTX
ORX
S3040
S3044 16 Rx S3083 Tx
16
16
S3040
ORX
OTX
Network Interface Processor
1
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S3083 SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 2 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates.
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
part of each STS-N signal is an optical carrier level-N signal (OC-N). The S3083 chip supports the OC-48 data rate (2.488 Gbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-48 consists of 144 transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pattern of 144 overhead and 4176 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Figure 2. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Path layer Line layer Section layer
Path layer Line layer Section layer
Photonic layer
Photonic layer
End Equipment
Fiber Cable End Equipment
Table 1. SONET Signal Hierarchy
Elec.
STS-1 STS-3 STS-12 STS-24 STS-48
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made up of N byte-interleaved STS-1 signals. The optical counter-
CCITT
STM-1 STM-4 STM-8 STM-16
Optical Data Rate (Mbps)
OC-1 OC-3 OC-12 OC-24 OC-48 51.84 155.52 622.08 1244.16 2488.32
Figure 3. STS-48/OC-48 Frame Format
A1 A1
9 Rows
A1 A1 48 A1 Bytes
A2 A2
A2 A2 48 A2 Bytes
Transport Overhead 144 Columns 144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns 4176 x 9 = 37,584 bytes
s
125 sec
2
s
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER S3083 OVERVIEW
The S3083 transmitter implements SONET/SDH serialization and transmission functions. The block diagram in Figure 4 shows basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip includes parallel-to-serial conversion and system timing. The system timing circuitry consists of a high-speed phase detector, clock dividers, and clock distribution throughout the front end. The sequence of operations is as follows:
S3083
Transmitter Operations: 1. 16-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Internal clocking and control functions are transparent to the user. Details of the data timing can be seen in Figure 7, 18, and 19. Suggested Interface Devices
AMCC AMCC S3040 S3044 OC-48 Clock Recovery Device OC-48 Receiver
Figure 4. S3083 Functional Block Diagram
DLEB LLDP/N LLCLKP/N LLEB 16 16:1 PARALLEL TO SERIAL M U X D LSDP/N TSDP/N
PIN[15:0] PICLKP/N
LSCLKP/N M2 U X TSCLKP/N PCLKP/N
PHINIT
TIMING GEN PHERR
TESTEN CLOCK DIVIDER and PHASE DETECTOR REFCLKP/N RSTB CAP1/2 2
LOCKDET
155MCK
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S3083 S3083 ARCHITECTURE/FUNCTIONAL DESIGN
MUX OPERATION
The S3083 performs the serializing stage in the processing of a transmit SONET STS-48 bit serial data stream. It converts the byte serial 155.52 Mbyte/sec data stream to bit serial format at 2.488 Gbps. Diagnostic loopback is provided (transmitter to receiver), and Line Loopback is also provided (receiver to transmitter). A high-frequency bit clock is generated from a 155.52 MHz frequency reference by using a frequency synthesizer consisting of an on-chip phaselocked loop circuit with a divider, VCO and loop filter.
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Timing Generator
The Timing Generator function, seen in Figure 4, provides two separate functions. It provides a byte rate version of the TSCLK, and a mechanism for aligning the phase between the incoming byte clock and the clock which loads the parallel-to-serial shift register. The PCLK output is a byte rate version of TSCLK. For STS-48, the PCLK frequency is 155.52 MHz. PCLK is intended for use as a byte speed clock for upstream multiplexing and overhead processing circuits. Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3083 device. In the parallel-to-serial conversion process, the incoming data is passed from the PICLK byte clock timing domain to the internally generated byte clock timing domain, which is phase aligned to the TSCLK. The Timing Generator also produces a feedback reference clock to the Phase Detector. A counter divides the synthesized clock down to the same frequency as the reference clock REFCLK.
Clock Divider and Phase Detector
The Clock Divider and Phase Detector, shown in the block diagram in Figure 4, contains monolithic PLL components that generate signals required to drive the loop filter. The REFCLK input must be generated from a differential LVPECL crystal oscillator which has a frequency accuracy of better than the value stated in Table 7 in order for the VCOCLK frequency to have the same accuracy required for operation in a SONET system. In order to meet the 0.01 UI SONET jitter specifications, the maximum reference clock jitter must be guaranteed over the 12 kHz to 20 MHz bandwidth. For details of reference clock jitter requirements, see Table 2. The on-chip phase detector, which compares the phase relationship between the VCO input and the REFCLK input, drives the loop filter.
Parallel-to-Serial Converter
The Parallel-to-Serial converter shown in Figure 4 is comprised of a FIFO and a parallel-to-serial register. The FIFO input latches the data from the PIN[15:0] bus on the rising edge of PICLK. The parallel-toserial register is a loadable shift register which takes its parallel input from the FIFO output. An internally generated divide by 16 clock, which is phase aligned to the transmit serial clock as described in the Timing Generator description, activates the parallel data transfer between registers. The serial data is shifted out of the parallel-to-serial register at the TSCLK rate.
Table 2. Reference Jitter Limits
Maximum Reference Clock Jitter in 12 kHz to 20 MHz Band 1 ps rms Operating Mode STS-48
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER FIFO
A FIFO is added to decouple the internal and external (PICLK) clocks. The internally generated divide by 16 clock is used to clock out data from the FIFO. PHINIT and LOCKDET are used to center or reset the FIFO. The PHINIT and LOCKDET signals will center the FIFO after the third PICLK pulse. This is in order to insure that PICLK is stable. This scheme allows the user to have an infinite PCLK to PICLK delay through the ASIC. Once the FIFO is initilized, the PCLK to PICLK delay can have a maximum drift as specified in Table 21.
S3083
generated clock. When a potential setup or hold time violation is detected, the phase error goes High. When PHERR conditions occur, PHINIT should be activated to recenter the FIFO (at least 2 PCLK periods). This can be done by connecting PHERR to PHINIT. When realignment occurs one to three bytes of data will be lost. The user can also take in the PHERR signal, process it and send an output to PHINIT in such a way that idle bytes are lost during the realignment process. PHERR will go inactive when the realignment is complete. (See Figure 8.)
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. The differential serial output clock and data from the transmitter (LSCLK and LSD) is routed to the input of companion device in place of the normal data stream (RSCLK and RSD).
FIFO Initialization
The FIFO can be initialized in one of the following three ways: 1. During power up, once the PLL has locked to the reference clock provided on the REFCLK pins, the LOCKDET will go active and initialize the FIFO. 2. When RSTB goes active, the entire chip is reset. This causes the PLL to go out of lock and thus the LOCKDET goes inactive. When the PLL reacquires the lock, the LOCKDET goes active and initializes the FIFO. Note: PCLK is held reset when RSTB is active. 3. The user can also initialize the FIFO by giving a positive edge on PHINIT. During the normal running operation, the incoming data is passed from the PICLK timing domain to the internally generated divide by 16 clock timing domain. Although the frequency of PICLK and the internally generated clock is the same, their phase relationship is arbitrary. To prevent errors caused by short setup or hold times between the two timing domains, the timing generator circuitry monitors the phase relationship between PICLK and the internally
Line Loopback
The Line Loopback circuitry consists of alternate clock and data output drivers. For the S3083, it selects the source of the data and clock which is output on TSD and TSCLK. When the Line Loopback Enable input (LLEB) is inactive, it selects data and clock from the Parallel to Serial Converter block. When LLEB is active, it forces the output data multiplexer to select data and clock from the LLD and LLCLK inputs, and a receive-to-transmit loopback can be established at the serial data rate.
TSCLK Powerdown
The user is advised not to connect pins 56, 57, 58 and 59 if TSCLKP/N output is not used. This should be done to reduce the power and to get the best results on the TSD output.
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S3083
Table 3. Input Pin Assignment and Descriptions
Pin Name PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PICLKP PICLKN Level SingleEnded LVPECL I/O I Pin # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 22 21
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Description Parallel Data Input. A 155.52 Mbyte/sec word, aligned to the PICLK parallel input clock. PIN[15] is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). PIN[0] is the least significant bit (corresponding to bit 16 of each PCM word, the last bit transmitted). PIN[15:0] is sampled on the rising edge of PICLK.
Diff. LVPECL
I
Parallel Input Clock. A 155.52 MHz nominally 50% duty cycle input clock, to which PIN[15:0] is aligned. PICLK is used to transfer the data on the PIN inputs into a holding register in the parallel-to-serial converter. The rising edge of PICLK samples PIN[15:0]. Line Loopback Data. Inputs normally provided from a companion S3044 device. Used to implement a line loopback function in which the receive serial data and clock signals are regenerated and passed through the S3083 transmitter. Internally terminated. Line Loopback Clock. Inputs normally provided from a companion S3044 device. Used to implement a line loopback function in which the receive serial data and clock signals are regenerated and passed through the S3083 transmitter. Internally terminated. Test Clock Enable. Set high to bypass the VCO using the LLCLK inputs. This mode operates at 2.488 GHz. Reference Clock. Input used as the reference for the internal bit clock frequency synthesizer. Internally terminated and biased.
LLDP LLDN
Externally Biased Diff. LVPECL Externally Biased Diff. LVPECL LVTTL Internally Biased Diff. LVPECL LVTTL
I
14 15
LLCLKP LLCLKN
I
11 12
TESTEN REFCLKP REFCLKN
I I
13 78 77
DLEB
I
8
Diagnostic Loopback Enable. Active Low. When active, selects diagnostic loopback. When DLEB is inactive, LSD and LSCLK are powered down and inactive. When active, the diagnostic loopback clock, (LSCLK), and data (LSD) outputs are active. TSD remains active in both states of DLEB. Master Reset. Reset input for the device, active Low. During reset, PCLK and 155 MCK does not toggle. Phase Initialization. Rising edge will realign internal timing.
RSTB PHINIT
LVTTL LVPECL
I I
9 45
6
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 3. Input Pin Assignment and Descriptions (Continued)
Pin Name LLEB Level LVTTL I/O I Pin # 5 Description
S3083
Line Loopback Enable. Selects Line Loopback. When LLEB is active, the S3083 will route the data from the LLD/LLCLK inputs to the TSD/TSCLK output. Loop Filter Pins. Connections for external loop filter capacitor and resistors. (See Figure 9).
CAP1 CAP2
Analog
I
67 66
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S3083
Table 4. Output Pin Assignment and Descriptions
Pin Name TSCLKP TSCLKN TSDP TSDN PCLKP PCLKN LSDP LSDN Level Diff. CML Diff. CML Diff. LVPECL Low Swing Diff. CML Low Swing Diff. CML SingleEnded LVPECL LVTTL I/O O O O Pin # 57 56 55 54 23 24 6 7
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Description Transmit Clock Output. Transmit serial clock output that can be used to retime the TSD signal. Transmit Serial Data. Serial data stream signals, normally connected to an optical transmitter module. Parallel Clock. A reference clock generated by dividing the internal bit clock by sixteen. It is normally used to coordinate byte-wide transfers between upstream logic and the S3083 device. Loopback Serial Data. Serial data stream signals normally connected to a companion S3044 device for diagnostic loopback purposes. The LSD outputs are updated on the falling edge of the LSCLK. Loopback Serial Clock. Serial clock signals normally connected to a companion S3044 device for diagnostic loopback purposes. The LSD outputs are updated on the falling edge of the LSCLK. 155.52 MHz Clock Output. 155.52 MHz clock output from the clock synthesizer. This output should be connected to the reference clock input of the external clock recovery function (such as the S3040). Lock Detect. Goes Low after the PLL has locked to the clock provided on the REFCLK pins. LOCKDET is an asynchronous output. Phase Error Signal. Pulses high during each PCLK cycle for which there is a potential setup/hold timing violation between the internal byte clock and PICLK timing domains. PHERR is updated on the falling edge of the PCLK outputs.
O
LSCLKP LSCLKN 155MCK
O
1 2 20
O
LOCKDET
O
47
PHERR
SingleEnded LVPECL
O
43
8
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 5. Common Pin Assignment and Description
Pin Name COREGND COREVCC LVPECLVCC LVPECLGND TTLVCC TTLGND NC AVCC AGND DNC +3.3V GND Level GND +3.3V +3.3V GND +3.3V GND I/O Pin # 51, 61, Core Ground 63, 65, 75 50, 60, Core VCC 62, 64, 70 3, 16, 17, LVPECL VCC 41, 52, 59 4, 10, 18, LVPECL Ground 42, 53, 58 48 19 TTL VCC TTL Ground Description
S3083
46, 49, 76 Not Connected 69, 72, 74, 80 68, 71 73, 79 44 Analog VCC Analog Ground Do not connect
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S3083
Figure 5. S3083 Pinout 80 PQFP/TEP
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVCC AGND REFCLKP REFCLKN NC COREGND AVCC AGND AVCC AGND COREVCC AVCC AGND CAP1 CAP2 COREGND COREVCC COREGND COREVCC COREGND
LSCLKP LSCLKN LVPECLVCC LVPECLGND LLEB LSDP LSDN DLEB RSTB LVPECLGND LLCLKP LLCLKN TESTEN LLDP LLDN LVPECLVCC LVPECLVCC LVPECLGND TTLGND 155MCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
S3083
80 PQFP/TEP TOP VIEW
COREVCC LVPECLVCC LVPECLGND TSCLKP TSCLKN TSDP TSDN LVPECLGND LVPECLVCC COREGND COREVCC NC TTLVCC LOCKDET NC PHINIT DNC PHERR LVPECLGND LVPECLVCC
10
PICLKN PICLKP PCLKP PCLKN PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 6. 80 PQFP/TEP Package
S3083
BOTTOM VIEW TOP VIEW
Note: The S3083 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not appear in the area immediately under the package. This heatsink is electrically biased to the Vee potential of the S3083. For optimum thermal management, a foil surface at ground (or Vee if other than ground) is recommended immediately under the package, and connected with multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or other conductive interposer can be used to establish a good thermal dissipation path.
Table 6. Thermal Management
Device S3083
1. Add 0.20W for loopback active.
Max Power 1.56 W1
ja 26C/W
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S3083
Table 7. Performance Specifications
Parameter Nominal VCO Center Frequency Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle Reference Clock Rise & Fall Times -100 45 Min Typ 2.488
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Max
Units GHz
Conditions
+100 55 1.5
ppm % ns
20 ppm. Required to meet SONET output frequency specification.
20% to 80% of amplitude.
Table 8. Output Jitter Generation vs. Ambient Temperature in Still Air (Without Heatslug attached)
Temperature Voltage -40 C 25 C 70 C 85 C 3.1 0.006 0.007 0.008 0.008 Max. Jitter Generation 3.3 0.006 0.007 0.007 0.008 3.47 0.006 0.007 0.007 0.008 Unit V UI (rms) UI (rms) UI (rms) UI (rms)
Note: Data were taken with 100 sweeps on HP test equipment.
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 9. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on VCC with Respect to GND Voltage on any LVTTL Input Pin Voltage on any LVPECL Input Pin LVTTL Output Sink Current LVTTL Output Source Current ESD Rating1
1. Human body model.
S3083
Min -65 -0.5 -0.5 0
Typ
Max 150 VCC VCC VCC 8 8
Units C V V V mA mA V
Under 500
Table 10. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on VCC with Respect to GND Voltage on any LVPECL Input Pin 3.135 VCC -2 3.3 Min -40 Typ Max 85 130 3.465 VCC Units C C V V
Table 11. Power Consumption
Parameter ICC1, 2 ICC 3
1. Add 55 mA for loopback active. 2. TSCLK powered on. 3. TSCLK powered down.
Min
Typ 325 345
Max 450 405
Units mA mA
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S3083
Table 12. LVTTL Input/Output DC Characteristics
Symbol VIH VIL IIH IIL VOH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Min 2.0 0.0 Typ Max TTL VCC 0.8 50 -500 2.2 Unit V V A A V Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VIH = Min. VIL = Max. IOH = -100 A VIH = Min. VIL = Max. IoL = 4 mA
VOL
Output Low Voltage
0.5
V
Table 13. Differential CML Output DC Characteristics
Parameter VOL VOH VOUTDIFF Clock VOUTSINGLE Clock VOUTDIFF Data VOUTSINGLE Data Description CML Output LOW Voltage CML Output HIGH Voltage CML Serial Output Differential Voltage Swing CML Serial Output Single-ended Voltage Swing CML Serial Output Differential Voltage Swing CML Serial Output Single-ended Voltage Swing Min VCC -0.95 VCC -0.35 700 350 800 400 Typ Ma x VCC -0.55 VCC -0.10 1400 700 1400 700 Units V V mV mV mV mV Condition 100 line-to-line. 100 line-to-line. 100 line-to-line. See Figure 20. 100 line-to-line. See Figure 20. 100 line-to-line. See Figure 20. 100 line-to-line. See Figure 20.
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 14. Low Swing Differential CML Output DC Characteristics
Parameters VOL VOH VOUTDIFF VOUTSINGLE Description Loopback CML Output LOW Voltage Loopback CML Output HIGH Voltage Loopback CML Serial Output Differential Voltage Swing Loopback CML Serial Output Single-ended Voltage Swing Min VCC -0.55 VCC -0.25 360 180 Typ Max VCC -0.25 VCC -0.05 800 400 Units V V mV mV
S3083
Conditions 100 line-to-line. 100 line-to-line. 100 line-to-line. 100 line-to-line.
Table 15. Internally Biased Differential LVPECL Input DC Characteristics
Parameters VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min 300 150 80 100 Typ Max 1200 600 120 Units mV mV Conditions See Figure 20. See Figure 20.
Table 16. Externally Biased Differential LVPECL Input DC Characteristics
Parameters VIL VIH VINDIFF VINSINGLE RDIFF Description LVPECL Input LOW Voltage LVPECL Input HIGH Voltage Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min VCC -2.000 VCC -1.20 300 150 80 100 Typ Max VCC -0.25 VCC -0.05 1200 600 120 Units V V mV mV See Figure 20. See Figure 20. Conditions
Table 17. Differential LVPECL Input DC Characteristics
Parameters VIL VIH VINDIFF VINSINGLE Description LVPECL Input Low LVPECL Input High Differential Input Voltage Swing Single Ended Input Voltage Swing Min VCC -2.0 VCC -1.2 400 200 Typ Max VCC -0.5 VCC -0.3 2000 1000 Units V V mV mV See Figure 20. See Figure 20. Comments
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S3083
Parameters VOUTSINGLE VOUTDIFF VOH VOL Description Single Ended Output Voltage Swing Differential Output Voltage Swing Output High Voltage Output Low Voltage
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Min 400 800 VCC -1.15 VCC -1.95 Typ Max 950 1900 VCC -0.60 VCC -1.45 Units mV mV V V Comments 220 to GND and 100 line-to-line. 220 to GND and 100 line-to-line. 220 to GND and 100 line-to-line. 220 to GND and 100 line-to-line.
Table 18. Differential LVPECL Output DC Characteristics
Table 19. Single Ended LVPECL Input DC Characteristics1
Parameters Description Min VCC -2.30 VIL PECL Input Low Voltage VCC -2.30 VCC -1.02 VIH PECL Input High Voltage VCC -1.22 Input High Current Input Low Current -0.5 VCC -0.57 20 V A A Guaranteed at -40 C. VCC -1.50 VCC -0.57 V V Guaranteed at -40 C. Guaranteed at 85 C. Typ Max VCC -1.44 Units V Conditions Guaranteed at 85 C.
IIH IIL
1. The AMCC LVPECL inputs are non-temperature compensated I/O which vary at 1.3 mV/C
Table 20. Single Ended LVPECL Output DC Characteristics
Parameters VOL VOH Description PECL Output Low Voltage PECL Output High Voltage Min VCC -2.2 VCC -1.2 Typ Max VCC -1.5 VCC -0.65 Units V V Conditions 220 to GND, 82 to Vcc, 130 to GND. 220 to GND, 82 to Vcc, 130 to GND.
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 7. Line Loopback Input Timing Diagram
S3083
LLCLKP tSLLD LLDP/N tHLLD
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
Table 21. AC Transmitter Timing Characteristics
Symbol Description LSCLK Frequency (nom. 2.48 GHz) LSCLK Duty Cycle PICLK Duty Cycle t S PIN t H PIN tP tS tH t S LLD t H LLD PIN [15:0] Set-up Time w.r.t. PICLKP PIN [15:0] Hold Time w.r.t. PICLKP TSCLK/LSCLK Low to TSD/LSD valid proagation delay TSD/LSD Set-up Time w.r.t. TSCLK/LSCLK TSD/LSD Hold Time w.r.t. TSCLK/LSCLK LLDP/N Set-up Time w.r.t. LLCLKP/N LLDP/N Hold Time w.r.t. LLCLKP/N 155 MCK Duty Cycle PCLKP/N Duty Cycle PCLK to PICLK drift after the FIFO is centered t SU th PHERR Set-up Time w.r.t. PCLK PHERR Hold Time w.r.t. PCLK 2 2 40 40 1.5 0.5 -100 105 105 100 100 40 45 60 55 5.2 100 Min Max 2.5 60 60 Units GHz % % ns ns ps ps ps ps ps % % ns ns ns
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S3083
Figure 8. Phase Adjust Timing
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
4-10 BYTE CLOCKS
2 BYTE CLOCKS
PHERR PHINIT
PCLK
PICLK
TRANSFER CLK (Internal)
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Figure 9. External Loop Filter
S3083
2.2 F 75 CAP1 75 CAP2
Figure 10. CML Output to +5V PECL Input AC Coupled Termination
+3.3V
0.01 F 100 0.01 F
+5V
S3083 TSDP/N TSCLKP/N
Figure 11. -5V Single Ended ECL Driver to S3083 Input AC Coupled Termination
-5.2V 0.01 F 330 -5.2V
+3.3V 82 130
+3.3V
ECL
S3083 PIN[15:0]
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S3083
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 12. +5V Differential PECL Driver to S3083 Input AC Coupled Termination
+5V 0.01F 330 3.3V 82
3.3V 82 130
+3.3V
330
0.01F 130
S3083 PICLKP/N
Figure 13. S3083 to S3083 Terminations
+3.3V
+3.3V
220 220 S3083 PCLKP/N
100
S3083 PICLKP/N
Figure 14. S3083 to S3040/50 Terminations
+3.3V 0.01 F 150 50 0.01 F
Vcc - 1.3V
+5V
Vcc - 1.3V
S3083 155MCK
S3040/50 REFCLK
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August 27, 1999 / Revision B
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 15. Single-Ended LVPECL Driver to S3083 Input AC Coupled Termination
S3083
Vcc 0.01F 300 0.01F
Vcc -0.70V (DC AVG)
+3.3V
60
Vcc -0.70V (DC AVG) Single-Ended Driver S3083 REFCLKP/N
Figure 16. S3083 to S3044 for Diagnostic Loopback
+3.3V
+3.3V
100
S3083 LSDP/N LSCLKP/N
S3044 LSDP/N LSCLKP/N
Figure 17. S3083 to Differential LVPECL
3.3V
82 220 220 130
82 130
S3083 PCLKP/N
August 27, 1999 / Revision B
21
S3083
Figure 18. AC Input Timing
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
PICLKP
tS PIN tH PIN
PIN[15:0]
1. When a set-up time is specified on LVPECL signals between an input and a clock, the set-up time is the time in picoseconds from the 50% point of the input to the 50% point of the clock. 2. When a hold time is specified on LVPECL signals between an input and a clock, the hold time is the time in picoseconds from the 50% point of the clock to the 50% point of the input.
Figure 19. Output Timing
TSCLKP/ LSCLKP
tP tS tH
TSD/LSD
Notes on High-Speed PECL Output Timing 1. When a set-up time is specified on differential LVPECL signals between an output and a clock, the set-up time is the time in picoseconds from the cross-over point of the output to the cross-over point of the clock. 2. When a hold time is specified on differential LVPECL signals between an output and a clock, the hold time is the time in picoseconds from the cross-over point of the clock to the cross-over point of the output.
Figure 20. Differential Voltage Measurement
V(+) VSWING V(-)
V(+) - V(-)
VD = 2 X VSWING
Note: V(+) - V(-) is the algebraic difference of the input signals.
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Ordering Information
PREFIX DEVICE PACKAGE
S3083
S - Integrated Circuit
3083
QT - 80 PQFP/TEP
X
Prefix
XXXX
Device
XX
Package
IS
O 90 0
RT
IFI
Applied Micro Circuits Corporation 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
E
D
1
CE
August 27, 1999 / Revision B
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